module Reg_ID_EX (
    input wire clk,
    input wire rst,

    input wire flush,
    input wire stall,

    input wire [31:0] ID_rd1,
    input wire [31:0] ID_rd2,
    input wire [4:0]  ID_RF_waddr,

    input wire [31:0] ID_pc,
    input wire [31:0] ID_pc4,

    input wire [31:0] ID_sext_ext,

    input wire [2:0] ID_npc_op,
    input wire ID_rf_we,
    input wire [1:0] ID_rf_wsel,

    input wire [4:0] ID_alu_op,
    input wire ID_alub_sel,
    input wire ID_alua_sel,

    input wire ID_ram_we,
    input wire [2:0] ID_Ld_op,
    input wire [2:0] ID_S_op,

    output reg [31:0] EX_rd1,
    output reg [31:0] EX_rd2,
    output reg [4:0] EX_RF_waddr,

    output reg [31:0] EX_pc,
    output reg [31:0] EX_pc4,

    output reg [31:0] EX_sext_ext,

    output reg [2:0] EX_npc_op,
    output reg EX_rf_we,
    output reg [1:0] EX_rf_wsel,

    output reg [4:0] EX_alu_op,
    output reg EX_alub_sel,
    output reg EX_alua_sel,

    output reg EX_ram_we,
    output reg [2:0] EX_Ld_op,
    output reg [2:0] EX_S_op
);

always @(posedge clk or posedge rst) begin
    if(rst) EX_rd1 <= 0;
    else if(flush || stall) EX_rd1 <= 0;
    else EX_rd1 <= ID_rd1; 
end

always @(posedge clk or posedge rst) begin
    if(rst) EX_rd2 <= 0;
    else if(flush || stall) EX_rd2 <= 0;
    else EX_rd2 <= ID_rd2; 
end

always @(posedge clk or posedge rst) begin
    if(rst) EX_RF_waddr <= 0;
    else if(flush || stall) EX_RF_waddr <= 0;
    else EX_RF_waddr <= ID_RF_waddr; 
end

always @(posedge clk or posedge rst) begin
    if(rst) EX_pc <= 0;
    else if(flush || stall) EX_pc <= 0;
    else EX_pc <= ID_pc; 
end

always @(posedge clk or posedge rst) begin
    if(rst) EX_pc4 <= 0;
    else if(flush || stall) EX_pc4 <= 0;
    else EX_pc4 <= ID_pc4; 
end

always @(posedge clk or posedge rst) begin
    if(rst) EX_sext_ext <= 0;
    else if(flush || stall) EX_sext_ext <= 0;
    else EX_sext_ext <= ID_sext_ext; 
end

always @(posedge clk or posedge rst) begin
    if(rst) EX_npc_op <= 0;
    else if(flush || stall) EX_npc_op <= 0;
    else EX_npc_op <= ID_npc_op; 
end

always @(posedge clk or posedge rst) begin
    if(rst) EX_rf_we <= 0;
    else if(flush || stall) EX_rf_we <= 0;
    else EX_rf_we<= ID_rf_we; 
end

always @(posedge clk or posedge rst) begin
    if(rst) EX_rf_wsel <= 0;
    else if(flush || stall) EX_rf_wsel <= 0;

    else EX_rf_wsel <= ID_rf_wsel; 
end

always @(posedge clk or posedge rst) begin
    if(rst) EX_alu_op <= 0;
    else if(flush || stall) EX_alu_op <= 0;
    else EX_alu_op<= ID_alu_op; 
end

always @(posedge clk or posedge rst) begin
    if(rst) EX_alub_sel <= 0;
    else if(flush || stall) EX_alub_sel <= 0;
    else EX_alub_sel<= ID_alub_sel; 
end

always @(posedge clk or posedge rst) begin
    if(rst) EX_alua_sel <= 0;
    else if(flush || stall) EX_alua_sel <= 0;
    else EX_alua_sel <= ID_alua_sel; 
end

always @(posedge clk or posedge rst) begin
    if(rst) EX_ram_we <= 0;
    else if(flush || stall) EX_ram_we <= 0;
    else EX_ram_we <= ID_ram_we; 
end

always @(posedge clk or posedge rst) begin
    if(rst) EX_Ld_op <= 0;
    // else if(flush || stall) EX_Ld_op <= 0;
    else EX_Ld_op <= ID_Ld_op; 
end

always @(posedge clk or posedge rst) begin
    if(rst) EX_S_op <= 0;
    // else if(flush || stall) EX_S_op <= 0;
    else EX_S_op <= ID_S_op; 
end




endmodule